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JESD204B subclass 1 ADI framework support for ADC AD6676 and DAC AD9136

Question asked by htrispel on May 17, 2018
Latest reply on May 18, 2018 by htrispel

For a new project we require deterministic latency (uncertainty <1ns) for the DAC --> ADC chain. For the DAC currently the AD9136 and for the ADC the AD6676 are set due to performance reasons. There is 1 DAC and 1 ADC for this signal chain (no MIMO design). The FPGA is a Xilinx ultrascale+ device.

 

a) Do we require JESD204B subclass 1 to meet the uncertainty goal or would subclass 0 be sufficient?

b) Are the two devices supported - or better already tested and qualified - by the ADI JESD framework?

c) Is the Xilinx JESD core additionally required?

d) Do I understand correctly that we need software to support the interface? I assume it would be ok to run it in a microblaze processor embedded in the FPGA?

 

Thanks in advance

Henning

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