Who knows how long it takes to get an answer from Analog Devices in this forum. I placed a question yesterday afternoon. My question is queue with other questions entered 2 weeks ago.

Who knows how long it takes to get an answer from Analog Devices in this forum. I placed a question yesterday afternoon. My question is queue with other questions entered 2 weeks ago.

Hello,

the issues was” General questions about ADF4110” with the description:

In the datasheet of ADF4110 is described, that a prescaler is included besides a 13 Bit B-counter. The values given of the prescaler are 8/9, 16/17, 32/33 and 64/65. Does it means that the prescaler divides the RF-In frequency in fractional way, e.g. RF-In = 180MHz -> Output of the prescaler by selecting 8/9 = 159.99998Mhz? What are the meanings of the units B, BP and A in the description of the prescaler on page 12 of the datasheet?

It was posted in engineering zone in the category RF and microwave.

We need a PLL in the frequency range between 140 – 180MHz and the RF must be divided by 14 Bit least.

Did I choose the wrong category for my question?

Regards

Holger Doering

See explanation below. ADIsimPLL is a very useful resource too, I recommend downloading it.

For narrow band applications, the channel spacing is narrow (typically < 5 MHz), and the feedback counter, N is high. Achieving high N values with small circuit is achieved by the use of a dual modulus P/P+1 prescaler, (figure 12) and allow N values to be computed with the calculation of N = PB+A, which using the example of an 8/9 prescaler, and an N value of 90, computes a value of 11 for B, and 2 for A. The dual modulus prescaler will divide by 9 for A, or two cycles, it will then divide by 8 for the remaining (B-A) or 9 cycles as described in table 1. The prescaler is generally designed using a higher frequency circuit technology such as bi-polar Emitter Coupled Logic (ECL) circuits, while the A & B counters can take this lower frequency prescaler output and can be manufactured with lower speed CMOS circuitry. This reduces circuit area and power consumption. Low frequency clean up PLLs like the ADF4002 above omit this prescaler.

*Figure 12. PLL with dual modulus N counter.*N value

P / P + 1

B value

A value

90

9

11

2

81

9

10

1

72

8

9

0

64

8

8

0

56

8

7

0

48

8

6

0

40

8

5

0

32

8

4

0

24

8

3

0

16

8

2

0

8

8

1

0

0

8

0

0

Table 1. Dual modulus prescaler operation.

We generally try to respond to questions within 48 hours but are not always able to make that goal. Can you reference the question that you asked two weeks ago and I'll to get in touch with the responsible engineer to get a response to you?