I am looking for some insight to what I could be going wrong with writing to a zedboard DDR memory through the ADI AXI DMAC ip core. I am working off the AD9467_FMC reference project and the latest updates from the repo. The ADC is feeding an incremental counter to my DMAC core when it is then being written to the DDR address of 0x0800000. However as it can be seen in the attached word document (DDR Memory Read Out.docx) the data is not store sequentially, ie 0,1,2,3,4,5,6,... etc. All the numbers are there they are just out of order.
I have attached my control code (ADS42LB69.c/h) files that are used to control the DMAC. Reading from the ADC is done with adc_chb_capture(8192, 0x08000000) and the memory read is done with test_ddr_mem_read(8192, 0x08000000). Please refer to the first 4 hex values of the Rdata value as these are the ones that should be incrementing correction, the 4 least significant hex values are for another channel that is disabled (same issue happens there as well).
The IP core has the following settings,
Any help would be appreciated, thanks.