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AD7124-4 Single Conversion settling time problem

Question asked by Di0f on May 15, 2018
Latest reply on May 23, 2018 by Di0f

Hello, I'm currently working with AD7124-4 in Single Conversion mode and I'm trying to make it faster.
On page 80 of datasheet:

Single conversion mode. When single conversion mode is selected, the ADC powers up and performs a single conversion on the selected channel. The conversion requires the complete settling time of the filter.

Go to page 54 and for filter SINC4:

The settling time for the sinc4 filter is equal to

Tsettle = (4 * 32 * FS[10:0] + Dead_Time)/Fclk
where Dead_Time = 61 when FS[10:0] = 1, and 95 when FS[10:0] > 1.

So, by following code where I've used your API:

            ad7124_regs[AD7124_ADC_Control].value |=
            AD7124_ADC_CTRL_REG_POWER_MODE(3) |
            AD7124_ADC_CTRL_REG_MODE(1) |
            AD7124_ADC_CTRL_REG_REF_EN;    
            ret = AD7124_WriteRegister(ad7124_handler, ad7124_regs[AD7124_ADC_Control]);


            // CHANNEL0   
            ad7124_regs[AD7124_Channel_0].value |=

            AD7124_CH_MAP_REG_CH_ENABLE |
            AD7124_CH_MAP_REG_SETUP(0x00) |
            AD7124_CH_MAP_REG_AINP(0x00) |
            AD7124_CH_MAP_REG_AINM(0x01);
            ret = AD7124_WriteRegister(ad7124_handler, ad7124_regs[AD7124_Channel_0]);  
            
            // CONFIG0
            ad7124_regs[AD7124_Config_0].value |=
            AD7124_CFG_REG_BIPOLAR |
            AD7124_CFG_REG_REF_SEL(2) |
            AD7124_CFG_REG_PGA(0);
            ret=AD7124_WriteRegister(ad7124_handler, ad7124_regs[AD7124_Config_0]);


            //FILTER0
            ad7124_regs[AD7124_Filter_0].value |=
            AD7124_FILT_REG_FILTER(0) |
            AD7124_FILT_REG_REJ60 |
            AD7124_FILT_REG_FS(8);
            ret = AD7124_WriteRegister(ad7124_handler, ad7124_regs[AD7124_Filter_0]);

I'm expecting T_settle = (4 * 32 * 8 + 95)/614 400 = 0,0018212890625, but when I'm trying to make more than 10 measurements per second all conversions that come faster than t = 0.1 are get nothing in Data_Register (!RDY bit is on).
It seems like filter settings didn't change at all because ADC can not perform T_settle lesser than 0.0815 (80.15ms if FS[10:0] = 384 — default value).

Can someone explain me this issue? Maybe I've misunderstood the main concept of single conversion mode?
Any information would be helpful.
Regards.

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