We'll be using the -1300 MSPS version of this part and need to verify that the combinations of lane rate, L, M, F, and DCM we intend to use are supported. Table 34 in the "Setting up the AD9695 Digital Interface" section of the AD9695 datasheet (Rev. A) appears to be specific to the -625 MSPS part, not the -1300 MSPS. Both example setup 1 and 2 in the datasheet use 1300 MSPS, but refer to combinations of values that don't actually exist in table 34.
Example 1 uses N'=16 and full bandwidth (DCM = 1) with 13 Gbps per lane, L=4, M=2, F=1. Looking up those parameters in table 34 gives "N/A" under supported decimation rates, and not 1.
Example 2 uses N'=16 and decimate-by-4 (DCM = 4) for two configurations:
1. 6.5 Gbps per lane, L=4, M=4, F=4
2. 13 Gbps per lane, L=2, M=4, F=4
Looking up those parameters in table 34 gives 1,2,3 for both configurations under supported decimation rates, but not 4.
For our application, we'd like to keep our lane rate constant and vary the L and M based on the decimation rate we select. Keeping the lane rate constant allows us to use the same clock frequency for our FPGA's transceiver and JESD204B IP core clock for all configurations. A/D sample rate = 1300 MSPS.
DCM = 1: Lane rate=6.5 Gbps, L=4, M=1 (1 real A/D), F=?
DCM = 2: Lane rate=6.5 Gbps, L=4, M=2 (1 complex I/Q), F=?
DCM = 4: Lane rate=6.5 Gbps, L=2, M=2 (1 complex I/Q), F=?
DCM = 8: Lane rate=6.5 Gbps, L=1, M=2 (1 complex I/Q), F=?
DCM = 16: Lane rate=6.5 Gbps, L=1, M=4 (2 complex I/Q), F=?
Are these combinations supported and what F values need to be used? If not, will any valid combinations of L and M achieve a constant line rate?