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AD9163 Multichip synchronization

Question asked by Splitter on May 14, 2018
Latest reply on May 23, 2018 by saberbf

Hi,

 

I am trying to achieve multichip synchronization for two AD9163s.
Until now, i have used the AD9163 without synchronization, it works perfectly.
I am using an Arria10 with the Altera JESD IP as TX JESD Transmitter.

 

My configuration is:
DACs CLK = 4915.2 MHz
DACs SYSREF = 0.640 MHz (Continuous sysref)

 

At this point, i was using the AD9163 without SYSREF, since they were unneeded when no synchronization requested. So i used to set register 0x3A to 0, so SYNC was in "Monitor Sync Mode" (SYNC_MODE = Register 0x03A, Bits[1:0]) = 0b00.
In this case, the JESD link establishment can happen any time.

 

Then I started to set register 0x3A to 1, so SYNC was in "Continuous Sync Mode" (SYNC_MODE = Register 0x03A, Bits[1:0] = 0b01).

 

If i understand the documentation correctly, JESD link establishment should now only occur on a sysref edge.
However this is not what I observe, the JESD link establishment still happen at any time:
I tried to configure DACs + FPGAs without sending any SYSREF edge, the JESD link was still established (for both DACs).
I retried this several time, by disabling/re-enabling the link, setting REG[0x300]:GENERAL_JRX_CTRL_0.LINK_EN to 0, then to 1, everytime JESD link was re-establish, without sending any sysref to DAC or FPGA. (REG[0x036]:SYSREF_COUNT was indeed at 0)
1)Is this the expected behaviour ?
What is the way, to start JESD alignment at the same time for both DACs ?

 


My startup procedure is:
* DAC CLKs turned ON
* FPGA JESD CLKs turned ON
* DAC0 turned ON
* DAC0 configured
* DAC1 turned ON
* DAC1 configured
* FPGA/DAC SYSREFs turned ON
2) Is this, the correct procedure to achieve multichip synchronization ?

 

3) What should I change to get multichip synchronization ?

 

Thanks

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