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ADV7391 SYNC amplitute setting

Question asked by Rani.fe Employee on May 13, 2018
Latest reply on May 14, 2018 by GuenterL

Hi,

 

Customer is using the adv7391. The sync amplitude signal does not flow from 0V to 300mV, for SD definition, it has some offset on it, of 40mV. See attached scope screen shot.

 

My question is if this can be corrected by adjusting the amplitude of the DAC or other.

 

The configuration of the part is as follows:

WHEN NTSC_INIT =>     -- NTSC

                                                ADDRESS <= i2c_wr_addr;

                                                CASE COUNTER IS

                                                  WHEN 0 =>   

                                                  SUBADDRESS <= X"17";          

                                                  DATA <= X"00";                       -- NO Soft Reset

                                                  WHEN 1 =>

                                                  SUBADDRESS <= X"00";          

                                                  DATA <= X"10";                       -- DAC1 ON, PLL ON     

                                                  WHEN 2 =>

                                                  SUBADDRESS <= X"01"; 

                                                  DATA <= X"00";                       -- Standard Definition Input Mode

                                                  WHEN 3 =>

                                                  SUBADDRESS <= X"02";          

                                                  DATA <= X"20";                       -- CVBS output on DAC 1 

                                                  WHEN 4 =>

                                                  SUBADDRESS <= X"80";          

                                                  DATA <= X"10";                       -- NTSC Mode, luma and chroma filters ON

                                                  WHEN 5 =>

                                                  SUBADDRESS <= X"82"; 

                                                  DATA <= X"CB";                      -- CVBS output with pedestal enabled

                                                  WHEN 6 =>

                                                  SUBADDRESS <= X"8A"; 

                                                  DATA <= X"0C";                      -- Slave Mode 2, HSYNC, VSYNC IN , -40 IRE      

                                                  WHEN 7 =>

                                                  SUBADDRESS <= X"8C";  

                                                  DATA <= X"1F";                         -- Fsc0                          

                                                  WHEN 8 =>

                                                  SUBADDRESS <= X"8D"; 

                                                  DATA <= X"7C";                        -- Fsc1

                                                  WHEN 9 =>

                                                  SUBADDRESS <= X"8E"; 

                                                  DATA <= X"F0";                         -- Fsc2

                                                  WHEN 10 =>

                                                  SUBADDRESS <= X"8F"; 

                                                  DATA <= X"21";                         -- Fsc3

                                                  WHEN 11 =>

                                                  DAC_state_type <= DO_BIT;

                                                  WHEN OTHERS =>

                                                  null;

                      END CASE;

 

Thanks,

Rani

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