I'm looking to use a BF706 at 400mhz core clock and 200mhz system clock
I read that the minimum signal length has to be 2 x sclk_time - 1.5, so i presume that'll be 2 x ( 1/200 ) - 1.5 or 8.5 ns
How fast would I be able to poll/inspect any gpio pin?
since the coreclock is 2x the system clock, when will the signal actually be read in, when a mmio read is issued? would it necessarily be 3 cclk cycles later in order to synchronize with system clk?
If i were to write to the gpio pin, how long does that take to execute, and for the pin to actually change?
I also noticed there's a few mmio registers that get set on rising, falling edges or both, do these get reset? or do I have to manually reset them to detect another such event? (and is this done asynchronously? from the core? or is it clocked in at system clock)
I'm looking to poll a 25mhz signal (open drain style, possibly by using the suggested procedure of, only set port as output and input leaving port i/o value alone) This is a pretty standard 2 wire protocol, with a clock at 25mhz, and data to be setup on the rising edge of clock, ready to be read on the falling edge, until the next rising edge clock. I presume e with a 40ns period, I will only have 20ns to read the signal and store it before the next bit comes in. Would this particular core be fast enough at 400 mhz cclk/200 mhz sclk ?