I've got the BF561 hooked up in frame sync loop back mode to an AD73311. I checked that the PF pins from the SPORT1 toggle the right pins on the AD73311 using a simple logic analyzer. I programmed the sport to use frame sync on each word and 16 bits long:
*pSPORT1_TCR2 = 0x000f; // 16 bit
*pSPORT1_RCR2 = 0x000f; // data
*pSPORT1_TCR1 = TFSR; // frame sync each word, falling edge sample
*pSPORT1_RCR1 = RFSR; // frame sync each word, falling edge sample
*pSPORT1_TCR1 |= TSPEN; // tx enabled
*pSPORT1_RCR1 |= RSPEN; // rx enabled
I sent 8 control words to the TX FIFO, then I enabled the AD73311 by raising the reset and SE lines. On the logic analyzer I see clock and frame sync, but no TX data from the sport. Since the SPORT is set up for external clock and frame sync, it should just start spewing what is in the FIFO. But the SDI line just sits at zero which the codec is perfectly happy to send back, so the SDO line sits at zero as well.
What bit needs to be flipped so the SPORT will spit out what is in the FIFO? I've tried a lot of combinations of reading and writing the sport but it really should just spew out when the first frame sync and clock pulse shows up. I hope it's obvious to somebody!