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Trouble finding the "frame clock"

Question asked by QIE1.38*10^-23 on May 10, 2018
Latest reply on May 25, 2018 by AdrianC

Hello All,

I'm trying to get the talk to an AD-FMCADC3-3BZ with the AD9625 chip on it. I want it to send the ila data to me as described in the JESD204B protocol. I am unsure about a few things though. I need to know exactly when to change the ~sync pin, how long to hold it, and when to send the SYS-REF signal. I have read the documentation and it says that the ~sync signal needs to be synchronized with the "frame clock". I then look for a definition for the "frame clock" and find nothing. I found the documentation put out by JEDEC and they say it is: "A signal used for sequencing frames or monitoring their alignment. " which is pretty useless. I have a clock which latches in the data from the adc and into the fpga. Lets call it the RXUSRCLK2.This clock is going at about 6.4 ns / tic. Another clock is going 5 ns / tic. Lets call it the system clock. There are other clocks generated by the QPLL and I can always slow one of these down. I am using Xilinix Virtex 7 VC707 to run this thing. I have gotten the SPI to work in both read and write modes so I have access to all the registers. Please let me know if you have dealt with these systems before. Some simulations showing the precise timing of these signals would be sufficient.