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About calibrating the 32 kHz Clock(ADPD108)

Question asked by omar_hong on May 10, 2018
Latest reply on May 10, 2018 by Buckley

according to datasheet:


Data sampling (32 kHz) clock frequency adjust. This register is used to calibrate the sample frequency of the device to achieve high precision on the data rate as defined in Register 0x12. Adjusts the
sample master 32 kHz clock by 0.6 kHz per LSB. For a 100 Hz sample
rate as defined in Register 0x12, 1 LSB of Register 0x4B, Bits[5:0], is
1.9 Hz. Note that a larger value produces


If sample rate set 21Hz,what hz of 1LSB of register 0x4B?


600/(32000/21)=0.393 Hz ? Is this correct ?