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ADV7403 configuration for RGB (VESA 1360x768 at 60 Hz) to 24 bit RGB out

Question asked by shanying on May 10, 2018
Latest reply on May 11, 2018 by Poornima

I configurate ADV7403 according to the ADI authority document(Component Processor Nonstandard Video Formats), but there is no output.

 

3.4. Example 4: VESA 1360x768 at 60 Hz (Pixel Clock = 85.5 MHz)

  1. Set PRIM_MOD and VID_STD to the 1024 x 768 at 75 Hz standard.

       PRIM_MODE[2:0] = 010;

       VID_STD[3:0]= 1110;

  1. Program the latch clock. Referring to Table 2 for 85.5 MHz gives:

       LATCH_CLK[3:0] = 0010;

  1. Program PLL_DIV_RATIO to give the required sampling pixel clock. Using Equation 1, an Hsync frequency of 47.712 KHz and a pixel clock of 85.5 MHz give:

       PLL_DIV_MAN_EN = 1;

       PLL_DIV_RATIO[11:0] = 1792dec = 700hex

       Program PLL_QPUMP to 101b and VCO Range to 11b (refer to Table 3).

  1. Use Equation 2 to calculate FR_LL[11:0].

       TLine period = (1/47.712 kHz) = 20.959 us

       T27 MHz = 37.037 ns

       FR_LL[11:0] = 566dec = 236 hex

As a result of combining these new register settings with the standard settings, the following I2C writes are obtained for the ADV740x (device address 42) 1360 x 768 at 60 Hz:

##CP RGB Graphics Special Modes##:1360×768 _@ 60.015Hz, 85.500MHz Out through DAC:

42 05 02 ; Prim_Mode =010b for GR

42 06 0E ; VID_STD=1110b for 1024x768 _@ 75

42 3A 21 ; set latch clock settings to 010b, Power Down ADC3

42 3B 80 ; Enable External Bias

42 3C 5D ; PLL_QPUMP to 101b

42 6A 00 ; DLL Phase Adjust

42 6B 82 ; Enable DE output, swap Pr Pb

42 73 90 ; Set man_gain

42 7B 14 ; AV CODES DISABLE, TURN OFF EAV and SAV CODES

42 87 E7 ; PLL_Div_Ratio to 1792

42 88 00 ; PLL_Div_Ratio to 1792

42 8A F0 ; VCO Range to 11b

42 8F 02 ; FR_LL = 566

42 90 36 ; FR_LL = 566

42 F4 3F ; Max Drive Strength

End

 

I am sure that the hardware is working.

 

Any help would be greatly appreciated.

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