I remember reading somewhere on the ADI wiki for the AD9361 that after enabling the FIR filter, the LVDS digital tune routine should be re-run. Is this the case? I cannot seem to locate that comment and explanation. Can someone please advise?
When enabling/disabling the FIR filter the data to clock relationship slightly changes.
Re-running the digital interface tuning when the FIR filter is enabled/disabled is an optimization to improve the timing margins. This can help with designs where the timing is marginal, e.g. if the data traces are not precisely matched.
Not that this only applies to automatic digital interface tuning. If you use manual interface timing settings and the timing meets the setup and hold requirements for all data traces as specified by the datasheets there is no need to change the settings when enabling/disabling the FIR filter.
You can refer to the below link for further details
Digital Interface Timing Verification [Analog Devices Wiki]
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