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ad9361 sync_in pin timing

Question asked by prashanth453 on May 9, 2018
Latest reply on May 16, 2018 by Vinod

Dear all,


I am taking the FMCOMMS5 reference design for synchronize the 2 AD9361 Devices,as per the data  provided in multiple ad9361 devices

Synchronizing multiple AD9361 devices [Analog Devices Wiki] 

They mensioned  as "The SYNC_IN pin on the AD9361 is driven directly from the FPGA, length matched to both AD9361 devices, so the edge hits both parts at the same time. "

In my case both sync in pins are routed to two different boards.means both are not at same distannce,inn order to match the both the sync pins distance try to implement the odelay2 component,but the sync pin of on board is in HR Bank ,for the HR bank we dont have a odelay2 primitive.

please suggest me the solution how to sync those AD9361 sync_in pins.