In a edge mount SMA connector to multilayer PCB transition, I use GCPW as my RF trace on the PCB, and the co-planar ground planes are on the top layer, and the bottom ground is on the second layer. Because the bottom ground does not have direct contact with the SMA connector, I expect that there is going to be excessive inductance at the transition. I simulated in HFSS, and it confirmed what I expected, but the SMA pin that gets soldered on the PCB also introduces capacitance, and HFSS TDR simulation also shows that. In the TDR simulation, more inductance shows up as high impedance(higher than 50ohms, inductive spike), and more capacitance shows up as lower impedance(lower than 50ohms, capacitive dip), and through time to space mapping, I can tell where excessive inductance and capacitance lives. But what is the best way to compensate for both? I tried to cut the bottom ground plane and increase the RF trace width and the transition. When I increased the trace width, the impedance at the transition lowers down toward 50ohms, but at the SMA pin region, it gets more capacitive(lower away from 5ohms). Opposite goes for cutting bottom ground plane, I saw more inductive spike and less capacitive spike, but the difference between the spike and the dip is always the same. I just cannot find a way to compensate for both.