I met some strange things recently when I debug ad9361,Questions are as follows
(1) configure ad9361 twice after power up,can change the internal delay of ad9631?
(2) According to the document ug570,change ad9361 tx frequency exceeds 100mhz, ad9361 need to vco calibration,rf dc calibration,tx quard calibration.But when I change tx frequency exceeds 100mhz,I do this above,I found that the frequency of the signal is not the same as the frequency I expected.
for example : the expected freq : 1400mhz
real freq : 1400.6mhz(tx rfpll locked)
Why is it?
(3)Does da's clk of ad9361 the same as THB3's clk? or clk frequency same,phase different?
(4)when I config ad9361 in lvds,2r2t ,fdd mode,data clk 50mhz ,I found ad9361 ad q delay i one sample point.Does Official website has ad9361 configuration program(vhdl or verilog,2r2t,lvds)?