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Configure BF50xF for a synchronous burst read from internal Flash

Question asked by climb2him on Dec 15, 2011
Latest reply on Jan 10, 2012 by Nabeel

I am trying to perform a synchronous burst read from FLASH using a BF506F Easy Kit and having difficulties.  I can do it when the FLASH is configured for asynchronous mode, but want to do in sychronous mode to do it faster.

 

What I want to do is as follows:

1. Initialize the DSP to be able to execute code from RAM or FLASH. - works when in asynchronous mode.

2. Using code executing from RAM reconfigure FLASH for a synchronous burst read.

3. Use the sync read to copy code from FLASH to program RAM.

4. change the FLASH back to asynchronous mode to be able to execute code either place.

 

I find I can make the copy using an MDMA transfer when in Async mode. When I try this in sync mode, the DSP crashes and VisualDSP has to disconnect. I've tried not using the MDMA, but reading two bytes directly from FLASH. This also doesn't work.  Here are some snippets from my code, where I just try to read from FLASH in sync mode:

 

#define EBIU_AMBCTL_SYNC_MODE   0x342C
/*              
* B0RDYEN  1
* B0RDYPOL 0 because set configuration register to 1
* B0TT      Bank Transition Time = b#11 for sync
* ST        Setup Time (2 - recommended)
* HT        Hold Time (ST+HT>25 ns for writes, 0 for Reads)
* RAT       Read Access Time (2* Xlatency = 2*4 = 8)
* WAT       Write Access Time (>45ns)
*/


     /* write to the FLASH configuration register */

   /* FLASH_BASE_ADDRESS + (configuration_register_value << 1) - from BF50x Hardware reference manual */
   uint16_t* pCrAddr = (uint16_t*) (0x20000000 | (0x00000060 << 1));


   *pCrAddr = 0x19B3;
   /* CR15 - 0 for sync mode
      CR14 - reserved
      CR13-11 = 010 - 2 clock latency
      CR10 =1 active high
      CR9 has to be programmed to 0.     
      CR8 has to be programmed to 1.
      CR7 has to be programmed to 1.
      CR6 has to be programmed to 1.
      CR5-4 are reserved
      CR3 has to be programmed to 0.
      CR2 through CR0 have to be programmed to b#011.*/


   /* Need to wait 2 bus cycles (2 WAT?). 1 WAT = 5 SCLKs; */
   ssync(); ssync(); ssync(); ssync(); ssync();
   ssync(); ssync(); ssync(); ssync(); ssync();
   ssync();


   *pEBIU_MODE = 3; /* synchronous FLASH mode */
    ssync();


   *pEBIU_AMBCTL = EBIU_AMBCTL_SYNC_MODE;
   ssync();



/* Try to read from FLASH */

uint16_t* pFlashAddr = (uint16_t*) &BlinkFlashLed;

uint16_t  temp;
temp = *pFlashAddr;   /***********CRASHES HERE ************/


 

I'm running the CCLK at 300 MHz and SCLK at 100 MHz.

 

Anyone have any suggestions?

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