I'm trying to use the ADN2812 to recover an FDDI stream. I’ve been following the reference design (AN-657) as well as AN-746 “Supporting FDDI with the ADN2812." I have the ADN2812 in lock to refclock mode and as long as the FDDI data is sufficiently scrambled, the ADN2812 retimes the data and everything works great.
I'm experiencing unexpected behavior though when our FDDI nodes send 'Q' symbols (sustained 0’s.) during connection attempts. I understand that sending long strings with no transitions wouldn’t work in Lock to Data mode, but from AN746, I assumed that configuring the part in Lock to RefClk mode would pass through such data. And I believe we have the part configured in Lock to RefClk correctly since the recovered clock that is on pins 25 and 26 is a solid 125Mhz at all times.
Still, sustained 0's cause our ADN2812 to pass through not 0's, but spurious bit transitions until eventually LOL asserts for ~50ms. This pattern repeats every ~200ms until the incoming stream is switched to sufficiently mixed data.
Is someone out there familiar with this chip? I can provide scope shots, schematic chunks, and register settings if anyone's interested.