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Does Digital Interface Timing verify I/O routes

Question asked by minersrevolt on May 4, 2018
Latest reply on May 7, 2018 by larsc

Hello,

 

We have used the AD9361 chip on a custom board very closely emulating the FMCOMMS3 board. The controller for this board is another custom board which is using a Zynq7020.

 

We have taken the ZedBoard demonstration design and removed the unnecessary parts of the design (HDMI, S/PDIF, etc) leaving only the barebones AD IP,

 

IE :

The DAC and ADC pack/upack and DMA engines

AXI_AD9361 IP

 

We are controlling the AD9361 in LVDS Mode (FDD only).

 

When powering up the board the AD9361 initializes using the SPI bus interface and then passes its timing interface verification, 

 

Output from ad9361_dig_interface_timing_analysis function in ad9361_conv.c :

 

CLK: 30720000 Hz 'o' = PASS DC0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f: 0:o . . . . o o o o o o o o o o o  1:o o o . . . o o o o o o o o o o  2:o o o o . . . o o o o o o o o o  3:o o o o o . . . o o o o o o o o  4:o o o o o . . . . o o o o o o o  5:o o o o o o o . . . o o o o o o  6:o o o o o o o . . . . o o o o o  7:o o o o o o o o . . . . o o o o  8:o o o o o o o o o . . . . o o o  9:o o o o o o o o o o . . . . o o  a:o o o o o o o o o o o . . . . o  b:o o o o o o o o o o o o . . . .  c:o o o o o o o o o o o o o . . .  d:o o o o o o o o o o o o o o . .  e:. o o o o o o o o o o o o o o .  f:. . o o o o o o o o o o o o o o
Digital Tuning Results from ad9361_dig_tune_delay with BE_MOREVERBOSE enabled :
SAMPL CLK: 25000000 tuning: RX   0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f: 0:o o o o o o o o o o o o o o o o  1:o o # # # # o o o o o o o o o o  SAMPL CLK: 40000000 tuning: RX   0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f: 0:o o o o o o o o o # # # # # o o  1:o # # # # # o o o o o o o o o o  SAMPL CLK: 61440000 tuning: RX   0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f: 0:o o o o # # # # # # # # # # # #  1:o # # # # # o o o o # # # # # o  SAMPL CLK: 25000000 tuning: TX   0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f: 0:# # o o o o o o o o o o o o o o  1:# # # # # # # # # # # # # # # #  SAMPL CLK: 40000000 tuning: TX   0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f: 0:# # o o o o o o o o o o # # # #  1:# # # # # # # # # # # # # # # #  SAMPL CLK: 61440000 tuning: TX   0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f: 0:# # o o o o o # # # # # # # # #  1:# # # # # # # # # # # # # # # #

However when we transmit the spectrum seen is completely invalid. 

Using the same custom AD9361 board attached to the ZedBoard FMC the spectrum is as expected.

 

Therefore the problem must lie in something done in the software or FPGA of the controller board OR in the routing between these two custom boards.

 

Of course that is a lot to debug so what I want to know mainly is if the results of the interface timing can be used to verify that the routing and timing between the boards is correct. Therefore eliminating the connections from the source of this erroneous transmit output.

 

The reason I want to verify this primarily is because the RX_CLK_IN LVDS pair was erroneously tied to a non-MCRR pin which is of course causing timing errors in the FPGA; however I wouldn't expect this to cause the transmit to fail...

 

This is a lot of information please let me know where I can be more specific if necessary. Thanks.

 

Edit : 

 

Attached the output that isn't formatting well here. 

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