AnsweredAssumed Answered

AD-FMCDAQ2-EBZ EVAL board Limitation

Question asked by gsaavedra on May 4, 2018
Latest reply on May 8, 2018 by larsc



Our customer is using your AD-FMCDAQ2-EBZ Eval board with an FPGA board from HTG-K800 FPGA eval board from HiTech Global Below are my customer requirements and they don't seem to be working on your board. We learned that you have an statement in the link below about clocking and it says.


“The JESD204 lane rates depend on the data-output/input-rates. On the AD-FMCDAQ2-EBZ both for the ADC and the DAC the lane-rate is equal to 10 times the data-rate.”


 Does this mean that your board is FIX to handle to  only  10*Fout  and  our customer requirement won't work even if we change settings in their FPGA board. 



Fadc = 1000MHz

Fadc Clk Div = 2


Two DDCs

Real input, complex output

Line Rate = 5Gbps

ADC output sample rate = 125MHz 


FYI: They are not using the DAC, they are evaluating a TI DAC and they wish they use ours and I'm working on this so by supporting on the ADC I hope to win our DAC as well.


Thank you in advance.


NOTE: This is very hot, please advise. We are in the process of give them the ADS7-V2 board and the AD9680-LF500EBZ board.