Using Subclass 0 getting 6 out of 8 lanes connected after checking through x471 register using a Zynq MPSOC+ board
Please tell me more about the setup. How did you configure the DAC? Are you using Analog Devices developed API to configure the DAC? I need to get more information on this.
Configured the DAC using the generated setup from the ACE software for the Subclass0 configuration. The transmission is done using the Xilinx JESD204Phy and a custom design for the Link and Transport Layers.
Please answer the following question in order for me to be able to better help you out:
I might need an snapshot of the ACE screen showing the DAC configuration.
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