I have developed a design that by FPGA ultrascale (xcku040-ffva1156-2) interface by JESD protocol the DAC AD9164
I have initialized the DAC device as reported into the related Analog Device data sheet (Rev C).
I can see by Xilinx ILA (Hardware Manager) tool that the FPGA tx transceiver are continuously sending the control character K28.5, but the "sync" signal from the DAC is always fix to LOW.
From the DAC i can read that the PLL is correctely locked; the Lane Rate of the FPGA and DAC are the same.
DAC clock: 1GHz
Registro 0x110 => 0x80 (8 lines; Interpolation Rate x 1)
- Lane_Rate = (20 x 1G x 1)/8 = 2.5 Gbps (that correspond on which setup to the FPGA transceiver).
The SERDES signal level input to the DAC is 250 mVpp
Can someone help me to understand why the sync signal stay fixed low ?