I have the following problem: using an FPGA, I send to the ADV7341 (mounted over the ADV734xEBZ Eval Board) a video stream (single pixel - 30 bit RGB) plus sync signals (VSYNCn e HSYNCn) with a reference clock of 27MHz in PAL format (according to the timing shown in the Figure 33 reported in the ADV7403 DATASHEET MANUAL - January 2007. In particular, lane period is 64us: 4.67us HSYNC Width + 5.11us HSYNC Back Porch + 53.33us Valid Pixel + 0.889us HSYNC Front Porch). So if I send a classic COLORBAR (white+yallow+blue+green+violet+red+black), the video generated from the ADV7341 shows all the frame excpet the white bar (i.e. the first bar). Nevertheless, the monitor detects correctly the input video stream as 720x576@50i. Using the LabView based tool, I have previously configured the ADV7341 using the Table 82 and Table 42 (PAL) reported on the ADV7341 datasheet.
Where is the problem?
Before, I send to the ADV7341 a video stream 1280x720@60p and video is generated correctly.