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AD9517 Jitter and AD9434 500 MSPS ADC

Question asked by AndyB on Dec 14, 2011
Latest reply on Dec 14, 2011 by MFelmlee

My application will have two AD9434 12-bit, 500 MSPS ADCs running in parallel.  The sample rate needs to be programmable in the range of 100 MHz - 500 MHz.  I'm considering the AD9517 clock generator since it is used on the AD9434 evaluation board.


I'm trying to understand the jitter characteristics of the AD9517.  The datasheet has tables for absolute and additive jitter.  I'll likely use an external VCXO followed by the dividers in the AD9517.  How do I estimate the total jitter?  Is this simply the absolute jitter or do I add the absolute and additive?


Is there another clock generator that I should consider that may be more appropriate for my application?


Note that the input reference to the clock generator will be provided by a FPGA so its frequency will be programmable.