We are using the AD9250 in our project. And our hdl-project is built according to the reference design offered by the ADI. In the reference design, I found the IP core UTIL_ADXCVR just support GTX/GTH high speed serial port. But the FPGA we are using only support the GTP port. So, is the IP core UTIL_ADXCVR customed by the IP Catalog in the Vivado? What should I do to the IP core UTIL_ADXCRE to make it support the GTP port?