There is a missing folder from the Evaluation Project Files at the following url that could help me in my comprehension to use the ADAS3022 hdl code:
https://wiki.analog.com/resources/fpga/altera/ced1z/adas3022 (tb folder that contains the sources of the core's test-bench)
Also I would like to ask if it is possible to have a more commented CED1Z_interface.v hdl code because I am terrible at this. I am struggling with the registers and local parameters section...
What I am trying to do is to interface my FMC acquisition card (using 4 ADAS) on an motherboard we developped (using a Kintex7 interfaced with a Q7)