What are important considerations while programming the PMCTL register (to configure the PLL) for SHARC processors?
1. The maximum value for CLKIN* PLLM must be satisfied depending on whether the INDIV bit is set or not.i. CLKIN*PLLM must be < 400MHz when INDIV = 0 (divisor 1)ii. CLKIN*PLLM must be < 800MHz when INDIV = 1 (divisor 2)
Example 1, Correct !!(CLKIN = 24.576MHz)ustat3 = PLLM20|INDIV;dm (PMCTL) = ustat3;// INDIV is enabled(CLKIN*PLLM = 491.52) is < 800
Example 2, Wrong!!(CLKIN = 24.576MHz)ustat3 = PLLM20|PLLD2|DIVEN;dm (PMCTL) = ustat3; //INDIV is not enabled(CLKIN*PLLM = 491.52) is >400
The core clock derived in both the above cases is 245.76 MHz, Example 2 is illegal because it does not confirm to the CLKIN* PLLM limit requirement.
2. Clear the DIVEN bit during the write to PMCTL register while placing the PLL in bypass mode (by setting the PLLBP bit to 1) or bringing it out of bypass mode (by clearing the PLLBP bit).
3. Set the DIVEN bit while setting the core clock to SDCLK ratio bit in PMCTL register
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