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AD7124-4 DOUT/RDY Pin Keeps Toggling

Question asked by Jim-CTI on Apr 30, 2018
Latest reply on May 7, 2018 by JellenieR

I am working on a new design using the AD7124-4 and the DOUT/RDY pin keeps toggling ON then OFF every 80 uSec or so. I have tried several configurations, but nothing seems to cause the toggling to stop. The device is connected as follows. All of the SPI pins (1, 2, 4, 24) connect to the corresponding SPI1 pins on a PIC uP, and all of the analog ins connect to signal sources.

I believe the SPI bus on the PIC is set up properly, but I can not get the AD7124 to respond.

 

Currently I am writing the ADC_Control register with the following configuration:

   0x01  Write ADC_Control

   0b00010000

   0b11000000

(I posted the ADC Control Register Bit Description below. (Mode 0 is Continuous)

 

I am holding the CS constantly low.

 

When I send a 0x45 Read ID, I get no response.

 

I did notice that the SYNC pin was floating and shorted it to the AVDD pin next to it.

 

Any help would be greatly appreciated.

Thanks,

Jim

 

Table 66. ADC Control Register Bit Descriptions (pg. 79)

BitsBit NameDescription
15:130These bits must be programmed with a Logic 0 for correct operation.
12DOUT_RDY_DELControls the SCLK inactive edge to DOUT/RDY high time. When DOUT_RDY_DEL is cleared, the delay is 10 ns minimum. When DOUT_RDY_DEL is set, the delay is increased to 100 ns minimum. This function is useful when CS is tied low (the CS_EN bit is set to 0).
11CONT_READContinuous read of the data register. When this bit is set to 1 (and the data register is selected), the serial interface is configured so that the data register can be continuously read; that is, the contents of the data register are automatically placed on the DOUT pin when the SCLK pulses are applied after the RDY pin goes low to indicate that a conversion is complete. The communications register does not have to be written to for subsequent data reads. To enable continuous read, the CONT_READ bit is set. To disable continuous read, write a read data command while the DOUT/ RDY pin is low. While continuous read is enabled, the ADC monitors activity on the DIN line so that it can receive the instruction to disable continuous read. Additionally, a reset occurs if 64 consecutive 1s occur on DIN; therefore, hold DIN low until an instruction is written to the device.
10DATA_STATUSThis bit enables the transmission of the status register contents after each data register read. When DATA_STATUS is set, the contents of the status register are transmitted along with each data register read. This function is useful when several channels are selected because the status register identifies the channel to which the data register value corresponds.
9CS_ENThis bit controls the operation of DOUT/RDY during data read operations. When CS_EN is cleared, the DOUT pin returns to being a RDY pin within nanoseconds of the SCLK inactive edge (the delay is determined by the DOUT_RDY_DEL bit). When set, the DOUT/RDY pin continues to output the LSB of the register being read until CS is taken high. CS must frame all read operations when CS_EN is set. CS_EN must be set to use the diagnostic functions SPI_WRITE_ERR, SPI_READ_ERR, and SPI_SCLK_CNT_ERR.
8REF_ENInternal reference voltage enable. When this bit is set, the internal reference is enabled and available at the REFOUT pin. When this bit is cleared, the internal reference is disabled.
7:6POWER_MODE

Power Mode Select. These bits select the power mode.
The current consumption and output data rate ranges are dependent on the power mode.
00 = low power.

01 = mid power.

10 = full power.

11 = full power.

5:2ModeThese bits control the mode of operation for ADC. See Table 67.
1:0CLK_SEL

These bits select the clock source for the ADC. Either the on-chip 614.4 kHz clock can be used or an external clock can be used. The ability to use an external clock allows several AD7124-4 devices to be synchronized. Also, 50 Hz and 60 Hz rejection is improved when an accurate external clock drives the ADC.
00 = internal 614.4 kHz clock. The internal clock is not available at the CLK pin.

01 = internal 614.4 kHz clock. This clock is available at the CLK pin.
10 = external 614.4 kHz clock.
11 = external clock. The external clock is divided by 4 within the AD7124-4.

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