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AD9361 HDL: Dual port half duplex mode (CMOS)

Question asked by liuf_stanford on Apr 27, 2018
Latest reply on Apr 29, 2018 by sripad

Does the the HDL at hdl/axi_ad9361.v at master · analogdevicesinc/hdl · GitHub  natively support CMOS dual port half duplex mode? UG-570 states that both P0 and P1 of the AD9361 will be used for simultaneous receive (or transmit) for a total of 24 bits, but I see only one 12-bit input bus in the physical interface specification (line 76).


Or do we have to write our own code?