I design a SigmaStudio schematic. Add lots of modules. And I listen to the output sound. NO!
Then I delete some modules and listening again. Until the sound is correct. Is this development efficiency too low?
When I think it's all right. I found that reading the "readback" module will affect the output sound. So I have to continue to delete some modules. Until the sound is correct.
Such a development is a great headache!
When the FS is 96K, the application only reach average 120 MIPS. If greater than 120, the sound is wrong.
Are there any better ways and ideas.
My target is ADSP-21489, 400MHz