I am using two AD9915 Eval boards to generate synchronized outputs at 2.856 GHz. I have some issues with synchronization, but for now I'm living with the fact that I can't reliable zero both phase accumulator registors simultaneously.
My objective is to use the profile registers to generate output pulses with an amplitude that varies with the profile bits. The frequency and phase are variable by program control, but are constant with the profile bit changes.
The idea is that I have two active profile bits. These bits are pulsed with pulses a few microseconds long. The bits are conditioned with a synchronizing circuit to make sure that the edges are synced to the sync_clk. In general the pulses overlap, so that I have four states.
00 All amplitudes are set to zero in Profile register 0
01 The output amplitude in Profile register 1 is selected.
10 Selects the amplitude in profile register 2
11 Selects the amplitude in profile register 3.
Thus, if PS0 is say 10 us long and PS1 is 9 us long delayed by 6 us relative to PS0 I get
0 amplitude intitially before the pulses are asserted. Then when PS0 is high I get Amplutide A1 for 6 us.
When PS1 goes high and PS0 is already high I get Amplutide A3 for 4 us. Then PS0 goes to zero and I get Amplitude A2 for 5 us. Then, when PS1 goes to zero the ampliude is again 0
In principle I need to adjust the timing so any length is possible for each state. Note that this sequence is a Gray Code sequence so onl one bit changes at a time and there are no glitch states.
The problem I have is that the profile registers do not always change on the trailing edge of each pulse. Everything appears to be working on the leading edge. When PS0 goes to 1 I get Profile register 1 and when PS1 goes to 1 I get profile register 3 if the pulses overlap. But at the end of PS0 or PS1 I do not get the correct state. Instead the previous amplitude continues. At the end of the pulses the amplitude does not always go to zero. This means the output stays the same until the next pulse. My high power rf system is designed for low duty factor so it will not be happy with a nearly continuous input.
I use a similar scheme successfully with AD9959 chips, where the profile bits select only the amplitude. In that case there is no conditoning of the profile bits to be synchronous with sync_clk.
Is this a timing issue? It's very frustrating because this system seems so simple on paper but has been a beast to tame in reality.