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AD7683 verilog parameter question

Question asked by AdrianC Employee on Apr 26, 2018
Latest reply on Apr 26, 2018 by AdrianC

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parameter real FPGA_CLOCK_FREQ  = 100;  // FPGA clock frequency [MHz]

parameter real ADC_CLOCK_FREQ   = 2.3;  // ADC clock frequency [MHz]

parameter real ADC_CYCLE_TIME   = 10;   // minimum time between two ADC conversions (Tcyc) [us]

parameter [9:0] ADC_CYCLE_CNT   = FPGA_CLOCK_FREQ * ADC_CYCLE_TIME - 1;

parameter [9:0] ADC_CLK_DIV     = FPGA_CLOCK_FREQ / ADC_CLOCK_FREQ / 2 - 1;

 

i just want to ask a question about the driver of AD7683,  as you can see, what does mean the parameter set  .   why it is 100 and 2.3, and you say MHz, i will be appreciate it if you can reply me as quickly as possible. please

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