Hi I'm using DAQ2 + ZC706 and no-OS version. I can now successfully configure ADC through SDK and read the 64/128 bits adc_data in axi_ad9680_fifo through ILA. My final goal is to continuously stream the ADC data at 1Gsps through ethernet. I have read through most of the threads here and still have the following few questions:
1. Is it possible to avoid data loss in the reference design using ZC706? Some says using the PL DDR3 memory resolves it but some mentioned there will still be data loss due to the throughput. (I don't need any DAC in my design so those portions can be taken out if necessary. )
2. What is the data flow after the adc_fifo block? From the connection it is transferring the data from the ADC core to the DDR3 controller, and also sending a 64 bits dma_wdata (what is this?) to the dma. Then how the data are being read from DDR3 and sending to the DMA?