Does the Quartus 17.0 AD9371 Arria10 project require external memory connected to the PL?
I see there is mention of external PL memory here:
hdl/a10soc_plddr4_assign.tcl at hdl_2018_r1 · analogdevicesinc/hdl · GitHub
and it seems that this file gets included in the a10 SoC make-file
hdl/Makefile at hdl_2018_r1 · analogdevicesinc/hdl · GitHub
But i'm not sure where (or if) it's used in the QSYS project? When looking at the adrv9371x_a10soc.qsf constraint files I dont think i see any pin mapping to the PL DDR but I could be wrong.
My colleague tried running IIO-Oscilloscope with the PL external memory disconnected and everything still seemed operational. This was tested on the 2017/2018 IMG file.