I am in trouble because I can not judge whether ADC data is normal or not.
CRC off. Output data SPI.
Of course It has enough setting time
DRDY and CS timing are OK.
All ADC channel is DC in.
I was taking the ADC Data following routine.
Address 0x008 0xFF :All channel daiable
Address 0x013 0x90 :SPI SALVE
Reading channel ADC data from SPI
Address 0x008 0x00 :All channel enable
Address 0x013 0x80 :SPI SLAVE off
Address 0x080 0x00 :All Channel enable
Address 0x012 0x08 :SPI_SYNC（bit0）0→1
This routine SPI ADC data was normal.
But wthout channel disable step, SPI ADC data was abnomal.
So ADC data was not constant.
0x080 resistor is DISABLE CLOCKS TO ADC CHANNEL REGISTER.
Though Sigam-Delta Modulation stop and ADC data remain last ADC data?
Why was ADC channel disable step skip abnormal?
Are there any other overlooks?