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ad9361 ref design clk scheme

Question asked by fahmed6 on Apr 24, 2018
Latest reply on Apr 27, 2018 by fahmed6

Hi,

 

I am trying to understand the clk scheme for the ad9361 and the IP cores i nthe ref design. I made a figure from what i understand so far for the TX path. clk1 is the clk for the interface as well as ad9361 core and fifo_out. clk2 is the clk for TX FIR filter, clk3 is the HB1 filter clk and so on. i assumed x2 interpolation in all the digital filters. I have a few questions regarding this:

 

1. Is my asusmtion correct that clk1 is common between the interface and the ad9361 core IP and FIFO out?

2. what is the clk freq of clk1?

3 clk2 =clk1*2,?

   clk3 =clk1*4,...

   clk5=clk1*16?

clk6(dac sampling)=clk5?

 

This is assuming x2 interpolation. Is my understanding correct?

 

Thanks in advance

Fahad

 

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