Presently I'm evaluating ADF4002 for our DDS-PLL hybrid architecture.
Due to some reason, the maximum hop distance is getting limited. In my loop configuration the maximum hop distance (one one frequency to the next) is limited to 170MHz. If I jump to a distance higher thatn this, the loop gets saturated to one of the extremes. This behavior is not seen in most of the PLLs. If the loop fails to acquire lock, them it will show an Fm modulation on the output and try to acieve lock. But in this case, it gets saturated to the upper voltage or lower voltage of the charge pump.
While investigating the causes of the problem, I came across the Anti-backlash pulse width in the phase detector section.
I want to study whether this has some influence on the locking performance (the non-linear behavior of the PLL).
I got some application notes regarding this which are more concentrated on the spurious behavior (backlash effect). But how can I study it's effect on the evaluation board of ADF4002??