I'm trying to simulate frequency synthesizer ranging from 5 GHz to 10 GHz with step size of 10 MHz. I have selected ADF41020 PLL IC and HMC587 VCO. And also i could not find HMC587 in ADIsimPLL 4.30.06 therefore i added its datasheet parameters in custom VCO with Kv 400MHz/V and input Capacitance 3pF and noise figure of -95dBC/Hz at 100KHz. i tried different loop bandwidth but this design did not lock. The design file is attached, kindly tell me what i'm doing wrong.