The program I wrote is not correct, no analog voltage.
We do not have a reference design, but this device has a simple interface. Make sure that the SYNC is connected to the chip select (CS) line of the SPI controller in FPGA. You should also control the RESET and LDAC pins with a GPIO controller. The RESET should be in high state and you should assert LDAC after each SPI transaction for at least one clock cycle.
Could you please look at the code for me?I can't find fault. thank you!
output wire RESET ;
reg sync_r= 1'b0;
reg sclk_r= 1'b0;
reg ldac_r= 1'b1;
reg i=8'd0 ;
always@(posedge clk )
assign RESET = 1 ;
Sorry, but we're not providing this kind of support.
But I can give you a few suggestions. Try to make a test bench for your design, and make sure that your design is working in simulation. Then when debugging in hardware you can use an embedded logic analyzer (ILA or SignalTap) to monitor the internal signals of your design.
Do you need to do register configuration when testing? My register input order,value:
software_reset_registe_cmd = 24'b0000_1111_0000_0000_0000_0000 ;
Control_register_cmd = 24'b0000_0100_0000_b0010_0010_1000;
The serial interface timing is ready, but what order should the register be written from SDI?My analog voltage won't come out.
Retrieving data ...