The AD4020 data sheet indicate that SINAD degrades 6.5dB at Fin=400kHz compared to Fin=100kHz. Will this be true if the input looks like it is sampled and held?
I have an application where I'm outputting 32 signals via a mux at 1.5 MHz to the ADC. The ADC is sampling them at 1.5MSPS, but each signal is DC. The signals could be uncorrelated so from that perspective the input to the ADC could look like Nyquist; however, since the signals are each DC they look like they are held with a S/H. The specification doesn't indicate if the degradation is from timing jitter, sample cap memory, etc so it is hard for me to know how performance will be affected with my application.