I discover that my pluto only streams the real part of complex signal to RF I don't understand why. I explain:
I'm using the pluto as standalone and using the python from iprium to run a simple loopback code.
In software part code I can assure everything is OK because debugging the FPGA with the ILA from Vivado I can see the samples going out from DMA buffer output and the interpolator.
is hard to understand the structure for the ad9361 core due the only documentation i found was this:
AD9361 HDL Reference Designs [Analog Devices Wiki] also in design for pluto is hard due it is a generic core for the ad9361 where instances for 2 input and 2 outputs are instantiated while the pluto only use 1x1.
The further point I was able to achieve was found the problem in the signal going out from the instance i_tx_channel_1(marked as blue in ILA). it has zero values while it should not due in interpolator out there are values so maybe is taking the signal from other point or is disabled.
The curious part is in the schematic (see pdf attached) from Vivado pluto project it
put the signal in from dma from 3 bit to 0 bit to ground while in the i_tx_channel_0 for the real part all bits are routed inside.
Maybe there is some configuration in design is not propagated correctly in design and the ad9361 core is with bad configuration.
I remember I had to create the pluto project from scratch running the source tcl instance by instance due I had errors with the make script so maybe some errors could be done generating the project in this way.
P.D. maybe this is not the place to put this question and I should publish it in other place. please let me know it.