Hello ADI guys,
My question comes from a interface design between FPGA and ad9122. In AD9122 datasheet, it mentions a dci delay function as below.
It seems that the dci signal treated as external source synchronous clock, and has some sampling uncertainty, which is interval of about 600ps window for normal case. And I see if we I change DCI delay register, and window will delay and expand a bit for different delay value.
However, when I read the following section, it's confused for me to understand the DCI function. My confusion is that when to increase the DCI delay, why the setup time also increases. In traditional design, we usually control the clock (DCI in this case) phase, and make sure the clock valid edge (i.e., sampling edge) arrives a bit later than data edge, which guarantee the setup time (constant) is satisfied. If I could adjust dci phase, and delay a bit, I wound tend to prevent the setup time issue. However, based on the datasheet, it seems DCI delay feature requires more setup time if I want to delay dci clock. (Is my understanding correct? ) If that's the case, what's the benefit of DCI delay feature?
It seems to be very confused to me. Could anyone guide the light to me? Thanks advance!