I am going through the refrence design for the ad9361 with zedboard. I am trying to understand how the PS communicates with the axi_ad9361 block in PL.
for example: the reference no-os design has the follwing code for resetting adc hdl block:
adc_write(phy, ADC_REG_RSTN, 0);
which is just a Xil_Out command to follwing:
Xil_Out32(AD9361_RX_0_BASEADDR + regAddr, data);
the addresses on the dirver side are defined as:
#define AD9361_RX_0_BASEADDR XPAR_AXI_AD9361_BASEADDR
#define XPAR_AXI_AD9361_BASEADDR 0x79020000
#define ADC_REG_RSTN 0x0040
I am tryint to understand how and where the base addresses are mapped to appropriate registers in HDL. On the HDL side i notice that the block axi_ad9361 is a slave axi block to the PS so i assume the configuration is wriiten on this channel. I can see in the address editor that the mempory mapped address for axi_ad9361 is 0x79020000 to 0x7902FFFF. But where and how is the offset ADC_REG_RSTN defined on the HDL side? I see that all the ADC/DAC configurations are handled in this way, so its important that we have an understanding of this.