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AD7656 CONVST timing

Question asked by cmoreno_uw on Apr 18, 2018
Latest reply on May 23, 2018 by jcolao



We're having an issue with the timing for conversions with the AD7656.  We need four channels simultaneously converted, so we tie CONVSTA and CONVSTB together (let's call that our CONVSTART signal).  We drive that CONVSTART signal with a hardware-generated 200 kHz signal  (i.e., the output of a hardware timer in our MCU).


Now, if the duty cycle of our CONVSTART signal is 50%, then every other conversion is skipped.  If we make it a 75% duty cycle, then it works.  I can't find anything in the datasheet that would explain why a 50% duty cycle square wave driving the CONVSTx inputs would not work.


What we think may be the logic that explains this behavior is that at the time that the conversion ends, the CONVSTx input must still be high, otherwise the conversion is aborted  (at 200 kHz, 50% duty cycle means CONVSTART falling edge occurs 2.5μs after the rising edge --- the conversion takes 3μs).  However, I can't find this requirement anywhere in the datasheet.   The only related parameter is t_10  (time from falling edge of CONVSTx until the next rising edge indicating a start of conversion), which is 25ns minimum --- a 50% duty cycle square wave does meet this requirement.


Can someone confirm what's going on / shed some light?   For reasons that I omit because they would make this message too long, it is beneficial for us to use a 50% duty cycle square wave  (so, it's not simply a matter of curiosity).