I am working on the development of a wireless communication based in a Xilinx Zynq-7000 FPGA connected to an evaluation AD-FMCOMMS3-EBZ board through a FMC connector.
I have been able to successfully support the Analog drivers in my platform and I am able to correctly execute the ADI IIO Oscilloscope to configure the transmission and reception parameters. What I am trying to do right now is to directly input data from a VHDL module in the dac_data_i0 and dac_data_q0 ports and try to receive this data in the adc_data_i0 and adc_data_q0 ports. At this time I use a feedback configuration where a cable connects the TX1A and the RX1A SMAs. The sampling clock that I am using to read and transmit the data is the l_clk from the axi_ad9361 IP core.
Unfortunately, I haven't been able in any configuration to read the exact data that I have input. My objective is to have a 12.5 Mbit/s transmission with a carrier frequency of 2.4 GHz.
Could you, please, suggest me any configuration or example design which can be helpful to implement this straightforward data exchange?
Thank you in advance and kind regards.