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AD-FMCDAQ2-EBZ axi_ad9680_fifo and axi_ad9144_fifo

Question asked by clearlove on Apr 17, 2018
Latest reply on Apr 18, 2018 by clearlove

When I open the FPGA design(axi_ad9680_fifo) ,I found that AD9680 data rate is 250MHz ,data width is 128 bits.And then the data is written to DDR3 .But when it is read from DDR3 to ARM(ZC706),the data rate is 100MHz ,data width is 64 bits.So,I want to kown whether a part of the data is lost?if not,how to understand it?

The same questin as the axi_ad9144_fifo.When the data is read from ARM ,the data rate is 100MHz ,the data width is 128bits.When the data is sent to AD9144 ,the data rate is 250MHz,the data width is 128bits.where does the extra data come from?

My English is poor,please forgive me.