Through learning the ADFMCDAQ2, I got some confusions need to confirm:
1.Is reference CLK from CLK+/CLK- the same with the DAC_CLK generated from AD9523-1, which has several options like 1GHz, 750MHz and so on?
2.Is the DACCLK for SERDES PLL the same with the one generated by the DAC PLL or directly sourced from CLK Rx?
3.Which register I can read to identify that if DAC PLL is being used ?
Appreciate the help from anyone has relevant background or experience.