For the past few weeks (too many weeks!), I have been trying to get the AD9162_FMC card working on the Xilinx ZCU102 eval card. I can operate the DAC in DC test mode, but not JESD.
I am using the AD916x_API-Rel1.0.0 API to initialise the DAC over SPI and the Xilinx JESD IP.
My DAC is configured as x8, 8,2,1,2 with a final DAC clock of 4.8GHz.
I get my expected tone out, but there are harmonics. I have an NCO driving SinCos to I and Q DACs. It appears only 4 of the 8 SERDES lines are driving the output, I can blank the input to the Xilinx JESD IP lanes 0:3 without affecting the RF output.
PRBS7, 15 and 31 tests give a pass on lanes 0:3, but a fail on lanes 7:8.
I cannot get the short TPL to work on any lane.
If I grab data directly from the DAC phy (using SNAPSHOT feature, which might not work?), I cannot correctly decode the 8B10B data, even the lanes that pass the PRBS test.
All lanes report locked, sync'd, good checksum etc - No interrupt errors.
I have done the lane inversions and swaps.
I am using an external 10MHz clock reference, all PLLs (on the FMC and FPGA) report locked and happy.
I really don't know where to turn# next :0(
Can anyone help?