We are using AD9361 based custom SDR board (designed based on fmcomms2). For evaluating our system performance, until now we were running in loop back mode an everything was alright. However, once we started using external RF signal generators and Spectrum Analyzers for validation purpose, we were surprised to see a drift in LO of both Tx and Rx paths of AD9361.
The frequency drift is the same for both Rx and Tx paths, and the drift is typically 0.5 MHz per 1 GHz. The drift is additive, i.e. when LO set to 1 GHz, the drift is 0.5 MHz when checked on spectrum analyzer, and when LO is set to 5 GHz, the drift is ~2.5 MHz (~5*0.5 MHz). We are using ADI provided bare metal software for controlling the SDR. The FPGA does have some changes, but nothing that can affect the the LO setting. We are using almost the same settings as the reference bare-metal software and the same crystal.
It would be great if someone could provide some leads or insights as to what might be causing this issue ?