Does the PVDD source determine the I/O voltage levels of the clocks or is that the DVDDIO source?
PVDD sources the internal PLL. This must be kept very clean for best performance. DVDDIO supply the output digital pins.
To make sure my understanding is correct. To connect the clocks to an FPGA, those signals will be at levels sourced by DVDDIO. PVDD only sources the internal PLL. Is this correct?
That is correct
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